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Silicon Labs /EFR32ZG23B010F512IM48 /MODEM_S /ANTDIVCTRL

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Interpret as ANTDIVCTRL

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1024IM40/MODEM_S/ANTDIVCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADPRETHRESH0 (DISABLE)ENADPRETHRESH 0 (ANTDIVDISCCA)ANTDIVDISCCA 0 (ANTDIVSELCCA)ANTDIVSELCCA

ENADPRETHRESH=DISABLE

Description

No Description

Fields

ADPRETHRESH

Preamble threshold
ENADPRETHRESH

Enable Preamble threshold

0 (DISABLE): Disable use of Preamble threshold after timing detection

1 (ENABLE): Enable use of Preamble threshold after timing detection
ANTDIVDISCCA

Antenna switch disable for CSMA
ANTDIVSELCCA

Antenna switch selection for CSMA

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data